As a Senior Design Verification Engineer, you will play a key role in verifying complex IC designs, ensuring functional correctness and performance compliance from specification to silicon. You will be responsible for developing and executing advanced verification methodologies, including UVM-based testbenches, functional coverage analysis, and debugging. This role offers an excellent opportunity to work on cutting-edge semiconductor technologies, collaborate with cross-functional teams, and contribute to innovation in the VLSI industry. Key responsibilities: Feature extraction from Specification and develop SoC/ASIC level verification plan. Architect and create verification environments using SystemVerilog and Universal verification methodology (UVM) for SoC/ASIC. Hands-on experience developing SystemVerilog OVM/UVM verification environment from scratch, including agents, monitors, drivers, and scoreboards is a plus. Lead a team in developing a self-checking Testbench using Verilog, and SystemVerilog to validate RTL designs in block and SoC levels. Lead a team in developing test cases and checkers according to the verification plan to achieve the desired functional and code coverage level. Tests and sequences development with constraint random stimulus. Develop and run block-level and system-level tests to verify system functionality. SVA generation and UVM RAL development flow and integration. Third-party (Synopsys, Cadence, Mentor) VIP integration. Lead engineers to develop scripts and run regression simulations. Experience in communicating with USA-based customer design teams is a plus. Qualifications and Skills: B.Sc. / M.Sc. in EEE, EECE and CSE Minimum of 5 years of experience Have good knowledge of the VLSI field. Vast knowledge of Analog and Digital Circuit Design and Analysis. Proficiency in Verilog / VHDL / SystemVerilog. A strong concept of any Procedural Programming Language such as C, SystemC, etc. Object-oriented programming concepts such as C++, Java, Python, etc. is a plus. Knowledge of CAD tools like Cadence IUS, Synopsys VCS, and Mentor Questa is a plus. Knowledge of Linux operating systems is a plus. Knowledge of Python, Perl, and Bash scripting is a plus. Benefits: Flexible working hours (8 AM to 4 PM, Mon – Fri) Friendly and creative work environment Fully Subsidized Lunch from the office Transportation facility (As per company policy) Yearly two festival bonuses Deadline: 15 February 2025 Job Location: Middle Badda, Dhaka This position offers a unique opportunity to work on state-of-the-art semiconductor designs in an environment focused on leadership, growth, and innovation. If you are passionate about physical design and thrive in a dynamic, technology-driven field, we encourage you to apply.