We are looking for some motivated and skilled Physical Design Engineers to contribute to cutting-edge semiconductor design projects. The role involves end-to-end physical design implementation, from floorplanning to GDSII, with a focus on optimizing power, performance, and area (PPA) metrics using advanced process technologies. Key Responsibilities: Perform RTL-to-GDSII implementation of physical design, including floorplanning, power planning, clock tree synthesis (CTS), placement and routing, engineering change orders (ECO), and logic equivalency checks (LEC). Conduct thorough static timing analysis (STA) to ensure timing closure while meeting design goals for performance and timing requirements. Analyze power and signal integrity issues, such as IR drop and noise, and implement optimization strategies to achieve power, performance, and area (PPA) targets. Drive sign-off processes, ensuring designs comply with foundry-specific physical and electrical verification rules, including design rule checks (DRC), layout versus schematic (LVS) verification, and electromigration/IR drop (EMIR) checks. Develop and maintain design methodologies and automation flows using efficient scripts and tools. Develop and maintain automation scripts using TCL, Python, or Perl to enhance physical design workflows and improve efficiency. Collaborate with cross-functional teams, including RTL design, verification, and DFT teams, to ensure seamless integration. Work across different time zones, addressing client requirements. Maintain detailed documentation of design processes and provide regular updates to project stakeholders. Quickly adapt to new technologies, workflows, and tools to stay ahead in advanced process technology nodes. Understand and align with client expectations while managing project timelines, schedules, and deliverables. Qualifications and Skills: B.Sc/M.Sc in Electrical and Electronic Engineering (EEE)/Computer Science and Engineering/Applied Physics or equivalent, with a focus on VLSI Design and Digital Electronics. At least two(2) years of hands-on experience with physical design tools and methodologies. Strong understanding of PnR workflows, including floorplanning, placement, CTS, and routing. Coursework or experience in VHDL and Verilog/SystemVerilog is highly desirable. Proficiency in programming languages such as C/C++ or any high-level programming language. Hands-on experience with Linux and scripting languages like Perl, Python, TCL, and Shell scripting. Strong analytical and debugging skills, with the ability to tackle complex design challenges. Excellent communication, collaboration, and teamwork skills. Self-motivated with innovative thinking, capable of multitasking under pressure. Benefits: Flexible working hours (8 AM to 4 PM, Mon – Fri) Friendly and creative work environment Fully Subsidized Lunch from the office Transportation facility (As per company policy) Unlimited tea & coffee Training to enhance skills Deadline: 15 February 2025 Job Location: Middle Badda, Dhaka This position offers a unique opportunity to work on state-of-the-art semiconductor designs in an environment focused on learning, growth, and innovation. If you are passionate about physical design and thrive in a dynamic, technology-driven field, we encourage you to apply.